1 standard products UT54ACS74/ut54acts74 dual d flip-flops with clear & preset datasheet november 2010 www.aeroflex.com/logic features ? 1.2 cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 14-pin dip - 14-lead flatpack ? UT54ACS74 - smd 5962-96534 ? ut54acts74 - smd 5962-96535 description the UT54ACS74 and the ut54acts74 contain two indepen- dent d-type positive triggered flip-flops. a low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. when preset and clear are inactive (high), data at the d input meeting the setup time requirement is transferred to the outputs on the positive-going edge of the clock pulse. following the hold time interval, data at the d input may be changed without affecting the levels at the outputs. the devices are characterized over full military temperature range of -55 c to +125 c. function table note: 1. the output levels in th is configuration are not guar anteed to meet the minimum levels for v oh if the lows at preset and clear are near v il maximum. in addition, this configuration is nonstable; that is, it will not persist when either preset or clear returns to its inactive (high) level. pinouts 14-pin dip top view 14-lead flatpack top view logic symbol inputs output pre clr clk d q q l h x x h l h l x x l h l l x x h 1 h 1 h h h h l h h l l h h h l x q o q o 1 2 3 4 5 7 6 14 13 12 11 10 8 9 clr1 d1 clk1 pre1 q1 q1 v ss v dd clr2 d2 clk2 pre2 q2 q2 1 2 3 4 5 7 6 14 13 12 11 10 8 9 v dd clr2 d2 clk2 pre2 q2 q2 clr1 d1 clk1 pre1 q1 q1 v ss q1 (5) (6) q1 q2 (9) (8) q2 (4) pre1 (3) clk1 (2) d1 (1) clr1 (10) pre2 (11) clk2 (12) d2 (13) clr2 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. s c1 d1 r
2 logic diagram pre clr clk q q d
3 operational environment 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the opera tional sections is not recommend ed. exposure to absolute maxi mum rating conditio ns for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
4 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c); unless otherwise noted, tc is per the temperature range ordered. symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 ? = 1mhz @ 0v 15 pf c out output capacitance 5 ? = 1mhz @ 0v 15 pf
5 notes: 1. functional tests are conducted in accordance with mil-std-883 with the followi ng input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any inpu t voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit bu t not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capac itance (per output buff er) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifi cation and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at a frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
6 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c); unless otherwise noted, tc is per the temperature range ordered. notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). 3. based on characterization, hold time (t h ) of 0ns can be assumed if data setup time (t su2 ) is > 10ns. this is guaran teed, but not tested. symbol parameter minimum maximum unit t phl clk to q, q 3 21 ns t plh clk to q, q 1 20 ns t plh pre to q 1 15 ns t phl pre to q 3 19 ns t phl clr to q 3 19 ns t plh clr to q 1 15 ns f max maximum clock frequency 71 mhz t su1 pre or clr inactive setup time before clk 5 ns t su2 data setup time before clk 5 ns t h 3 data hold time after clk 2 ns t w minimum pulse width pre or clr low clk high clk low 7 ns
7 packaging side-brazed packages
8 flatpack packages
9 UT54ACS74/ut54acts74: smd 5962 ***** ** * * * * lead finish: (notes 1 & 2) a = solder c = gold x = optional package type: x = 14-lead ceramic botto m-brazed dual-in-line flatpack c = 14-lead ceramic side-brazed dip class designator: q = qml class q v = qml class v device type: 01 drawing number : 96534 = UT54ACS74 96535 = ut54acts74 total dose: (notes 3 & 4) r = 1e5 rads(si) f = 3e5 rads(si) g = 5e5 rads(si) h = 1e6 rads(si) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, pa rt marking will match the lead finish and w ill be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening. for protot ype inquiries, contact factory. 4. device type 02 is only offered with a tid tolerance guarantee of 3e5 rads(si) or 1e6 rads(si) and is tested in accordance wi th mil-std-883 test method 1019 condition a and section 3.11.2 . device type 03 is only offered with a tid tolerance guarantee of 1e5 rads(si), 3e5 rads(si) , and 5e5 rads(si), and is tested in accordance with mil-std-883 test method 1019 condition a.
10 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex utmc microelectronic systems inc. (aeroflex) reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a product or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. aeroflex colorado springs - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hi-rel
|
